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URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 80

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Rev	Log message	Author	Age	Path
80	New version of the debug interface. Not finished, yet.	mohor	7605d 04h	/dbg_interface/trunk/bench/verilog/
75	Simulation files.	mohor	7666d 02h	/dbg_interface/trunk/bench/verilog/
73	CRC logic changed.	mohor	7666d 02h	/dbg_interface/trunk/bench/verilog/
63	Three more chains added for cpu debug access.	simons	7722d 04h	/dbg_interface/trunk/bench/verilog/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8200d 03h	/dbg_interface/trunk/bench/verilog/
38	Few outputs for boundary scan chain added.	mohor	8256d 04h	/dbg_interface/trunk/bench/verilog/
36	Structure changed. Hooks for jtag chain added.	mohor	8260d 03h	/dbg_interface/trunk/bench/verilog/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8400d 06h	/dbg_interface/trunk/bench/verilog/
15	bs_chain_o added.	mohor	8402d 07h	/dbg_interface/trunk/bench/verilog/
13	Signal names changed to lowercase.	mohor	8403d 08h	/dbg_interface/trunk/bench/verilog/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8404d 08h	/dbg_interface/trunk/bench/verilog/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8425d 04h	/dbg_interface/trunk/bench/verilog/
9	Working version. Few bugs fixed, comments added.	mohor	8429d 08h	/dbg_interface/trunk/bench/verilog/
6	Minor changes for simulation.	mohor	8430d 06h	/dbg_interface/trunk/bench/verilog/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8431d 04h	/dbg_interface/trunk/bench/verilog/
2	Initial official release.	mohor	8436d 04h	/dbg_interface/trunk/bench/verilog/

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