URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] - Rev 20

Rev	Log message	Author	Age	Path
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8292d 01h	/dbg_interface/trunk/rtl/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8304d 01h	/dbg_interface/trunk/rtl/
18	Reset signals are not combined any more.	mohor	8306d 10h	/dbg_interface/trunk/rtl/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8330d 00h	/dbg_interface/trunk/rtl/
15	bs_chain_o added.	mohor	8332d 01h	/dbg_interface/trunk/rtl/
13	Signal names changed to lowercase.	mohor	8333d 01h	/dbg_interface/trunk/rtl/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8334d 01h	/dbg_interface/trunk/rtl/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8354d 21h	/dbg_interface/trunk/rtl/
9	Working version. Few bugs fixed, comments added.	mohor	8359d 01h	/dbg_interface/trunk/rtl/
8	Asynchronous set/reset not used in trace any more.	mohor	8359d 23h	/dbg_interface/trunk/rtl/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8360d 21h	/dbg_interface/trunk/rtl/
2	Initial official release.	mohor	8365d 22h	/dbg_interface/trunk/rtl/