URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] - Rev 121

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Rev	Log message	Author	Age	Path
121	Port signals are all set to zero after reset.	mohor	7606d 23h	/dbg_interface/trunk/rtl/verilog/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7607d 03h	/dbg_interface/trunk/rtl/verilog/
117	Define name changed.	mohor	7608d 22h	/dbg_interface/trunk/rtl/verilog/
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7610d 05h	/dbg_interface/trunk/rtl/verilog/
106	Sensitivity list updated.	simons	7611d 03h	/dbg_interface/trunk/rtl/verilog/
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7611d 18h	/dbg_interface/trunk/rtl/verilog/
102	New version.	mohor	7611d 19h	/dbg_interface/trunk/rtl/verilog/
101	Almost finished.	mohor	7611d 20h	/dbg_interface/trunk/rtl/verilog/
100	* empty log message *	mohor	7612d 22h	/dbg_interface/trunk/rtl/verilog/
99	cpu registers added.	mohor	7612d 22h	/dbg_interface/trunk/rtl/verilog/
97	Working.	mohor	7614d 01h	/dbg_interface/trunk/rtl/verilog/
95	Temp version.	mohor	7614d 14h	/dbg_interface/trunk/rtl/verilog/
94	temp version. Resets will be changed in next version.	mohor	7615d 00h	/dbg_interface/trunk/rtl/verilog/
93	tmp version.	mohor	7616d 01h	/dbg_interface/trunk/rtl/verilog/
92	temp version.	mohor	7619d 05h	/dbg_interface/trunk/rtl/verilog/
91	tmp version.	mohor	7620d 00h	/dbg_interface/trunk/rtl/verilog/
90	tmp version.	mohor	7620d 19h	/dbg_interface/trunk/rtl/verilog/
89	temp4 version.	mohor	7622d 01h	/dbg_interface/trunk/rtl/verilog/
88	temp3 version.	mohor	7622d 20h	/dbg_interface/trunk/rtl/verilog/
87	tmp2 version.	mohor	7624d 01h	/dbg_interface/trunk/rtl/verilog/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] - Rev 121

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