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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] - Rev 143

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Rev Log message Author Age Path
143 Signals for easier debugging removed. igorm 7391d 01h /dbg_interface/trunk/rtl/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7391d 21h /dbg_interface/trunk/rtl/verilog/
139 New release of the debug interface (3rd. release). igorm 7394d 15h /dbg_interface/trunk/rtl/verilog/
138 Temp version before changing dbg interface. igorm 7400d 19h /dbg_interface/trunk/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7453d 01h /dbg_interface/trunk/rtl/verilog/
123 All flipflops are reset. mohor 7457d 22h /dbg_interface/trunk/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7460d 22h /dbg_interface/trunk/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7461d 02h /dbg_interface/trunk/rtl/verilog/
117 Define name changed. mohor 7462d 21h /dbg_interface/trunk/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7464d 04h /dbg_interface/trunk/rtl/verilog/
106 Sensitivity list updated. simons 7465d 02h /dbg_interface/trunk/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7465d 17h /dbg_interface/trunk/rtl/verilog/
102 New version. mohor 7465d 18h /dbg_interface/trunk/rtl/verilog/
101 Almost finished. mohor 7465d 19h /dbg_interface/trunk/rtl/verilog/
100 *** empty log message *** mohor 7466d 21h /dbg_interface/trunk/rtl/verilog/
99 cpu registers added. mohor 7466d 21h /dbg_interface/trunk/rtl/verilog/
97 Working. mohor 7468d 00h /dbg_interface/trunk/rtl/verilog/
95 Temp version. mohor 7468d 13h /dbg_interface/trunk/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7468d 23h /dbg_interface/trunk/rtl/verilog/
93 tmp version. mohor 7470d 00h /dbg_interface/trunk/rtl/verilog/

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