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[/] [dblclockfft/] [trunk/] [doc/] - Rev 19

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Rev	Log message	Author	Age	Path
12	Minor changes to both class (trimmed the portlist and revision history tables to match the text width), and the description of the io ports. Specifically, i_left, the port that is broken out and described, had mislabeled/misnumbered bits in the port list. As this is a minor change, I will not update the revision--although perhaps it should be.	dgisselq	3548d 13h	/dblclockfft/trunk/doc/
11	Here's the full first draft of the specification, now complete.	dgisselq	3548d 13h	/dblclockfft/trunk/doc/
10	I'm in the middle of building the spec. I've got most of the parts complete, but the figure diagraming an FFT stage is still in the works. I'm checking this in in the hopes that someone struggling to use this will find this initial draft of the specification useful enough to make their project work.	dgisselq	3549d 02h	/dblclockfft/trunk/doc/
3	The first upload of the s/w didn't take. Had it taken, the comment would've been: This is the first upload of the double clocked FFT software. While it should (roughly) be complete, a lot of work remains to be done--primarily in building test benches, modifying the interface of fftgen to make it more friendly, etc. In fact, the c++ code not only compiles, but the Verilog code it produces actually builds as well! Now, however, I have several test benches written, and have verified the unit functionality of the multiply, bit reversal stage, the dblstage (FFT len 2), and the qtrstage (FFT len 4). I then took a closer look at the multiply, discovered it failed at signed integers and rebuilt it. The new test bench tests the full 16-bit signed integer support properly. This leaves butterflies and generic FFT stages that still need test benches, as does the main (I)FFT program.	dgisselq	3552d 13h	/dblclockfft/trunk/doc/

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