URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] - Rev 88

Rev	Log message	Author	Age	Path
88	monitor: do not set sp on bootstrap	hellwig	3897d 22h	/eco32/trunk/
87	disk: master boot made compatible with monitor	hellwig	3898d 17h	/eco32/trunk/
86	disk: master boot made compatible with monitor	hellwig	3899d 08h	/eco32/trunk/
85	monitor: bootstrap parameters modified	hellwig	3899d 16h	/eco32/trunk/
84	monitor: bad address register added	hellwig	3899d 23h	/eco32/trunk/
83	simulator: individual help messages	hellwig	3900d 12h	/eco32/trunk/
82	simulator: change command @ -> #, better help for commands	hellwig	3900d 13h	/eco32/trunk/
81	hardware: cpu now has a bad address register	hellwig	3900d 22h	/eco32/trunk/
80	hwtests/xcptest now tests the bad address register too	hellwig	3900d 23h	/eco32/trunk/
79	hwtests (kbd): second timer added	hellwig	3901d 14h	/eco32/trunk/
78	simulator: tlbBadAddr register is now called mmuBadAddr	hellwig	3902d 17h	/eco32/trunk/
77	hardware: ucf file re-formatted	hellwig	3903d 20h	/eco32/trunk/
76	AUTHORS update	hellwig	3904d 11h	/eco32/trunk/
75	hardware: cpu now equal to port-15	hellwig	3904d 11h	/eco32/trunk/
74	when simulating the system include a console	hellwig	3904d 16h	/eco32/trunk/
73	use xess monitor when simulating the system	hellwig	3904d 17h	/eco32/trunk/
72	simulator: IRQ 0-3 explanation changed	hellwig	3904d 19h	/eco32/trunk/
71	simulator: IRQ 15 explanation added	hellwig	3904d 20h	/eco32/trunk/
70	hardware: two timers	hellwig	3905d 12h	/eco32/trunk/
69	hardware: timer counts clock cycles, counter is readable	hellwig	3905d 15h	/eco32/trunk/