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[/] [eco32/] [trunk/] [fpga/] - Rev 310

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Rev Log message Author Age Path
310 verilated mc implementation with and without trace hellwig 3249d 17h /eco32/trunk/fpga/
309 multicycle simulation of ECO32, using Verilator hellwig 3250d 17h /eco32/trunk/fpga/
308 multicycle design, suitable for being verilated hellwig 3250d 21h /eco32/trunk/fpga/
307 several tests got duration.dat files hellwig 3251d 11h /eco32/trunk/fpga/
304 Makefile updated hellwig 3254d 05h /eco32/trunk/fpga/
303 multicycle simulation control files added hellwig 3254d 06h /eco32/trunk/fpga/
302 tests updated hellwig 3254d 10h /eco32/trunk/fpga/
301 multicycle simulation source files added hellwig 3254d 18h /eco32/trunk/fpga/
300 memdelay experiment code looking better now hellwig 3254d 18h /eco32/trunk/fpga/
299 s3e-500 dac simulation corrected hellwig 3254d 19h /eco32/trunk/fpga/
298 xsa-xst-3 dac simulation corrected hellwig 3254d 20h /eco32/trunk/fpga/
297 memdelay experiment added hellwig 3254d 21h /eco32/trunk/fpga/
296 memspeed experiment added hellwig 3255d 09h /eco32/trunk/fpga/
295 tests for FPGA implementations hellwig 3255d 20h /eco32/trunk/fpga/
292 directory structure for FPGA implementations and simulations hellwig 3257d 11h /eco32/trunk/fpga/
291 avoid timing violations in DDR RAM circuit, new .bit files generated hellwig 3257d 12h /eco32/trunk/fpga/
290 Wishbone-compatible bus signals hellwig 3259d 12h /eco32/trunk/fpga/
289 new directory structure within fpga hellwig 3260d 09h /eco32/trunk/fpga/
288 new directory structure within fpga hellwig 3260d 10h /eco32/trunk/fpga/
287 new directory structure within fpga hellwig 3260d 10h /eco32/trunk/fpga/

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