URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] - Rev 313

Rev	Log message	Author	Age	Path
313	memory controller simulation 1	hellwig	3225d 03h	/eco32/trunk/fpga/
312	memory controller simulation 0	hellwig	3225d 04h	/eco32/trunk/fpga/
311	README updated	hellwig	3225d 05h	/eco32/trunk/fpga/
310	verilated mc implementation with and without trace	hellwig	3226d 02h	/eco32/trunk/fpga/
309	multicycle simulation of ECO32, using Verilator	hellwig	3227d 02h	/eco32/trunk/fpga/
308	multicycle design, suitable for being verilated	hellwig	3227d 06h	/eco32/trunk/fpga/
307	several tests got duration.dat files	hellwig	3227d 20h	/eco32/trunk/fpga/
304	Makefile updated	hellwig	3230d 14h	/eco32/trunk/fpga/
303	multicycle simulation control files added	hellwig	3230d 15h	/eco32/trunk/fpga/
302	tests updated	hellwig	3230d 19h	/eco32/trunk/fpga/
301	multicycle simulation source files added	hellwig	3231d 03h	/eco32/trunk/fpga/
300	memdelay experiment code looking better now	hellwig	3231d 03h	/eco32/trunk/fpga/
299	s3e-500 dac simulation corrected	hellwig	3231d 04h	/eco32/trunk/fpga/
298	xsa-xst-3 dac simulation corrected	hellwig	3231d 05h	/eco32/trunk/fpga/
297	memdelay experiment added	hellwig	3231d 06h	/eco32/trunk/fpga/
296	memspeed experiment added	hellwig	3231d 18h	/eco32/trunk/fpga/
295	tests for FPGA implementations	hellwig	3232d 05h	/eco32/trunk/fpga/
292	directory structure for FPGA implementations and simulations	hellwig	3233d 20h	/eco32/trunk/fpga/
291	avoid timing violations in DDR RAM circuit, new .bit files generated	hellwig	3233d 21h	/eco32/trunk/fpga/
290	Wishbone-compatible bus signals	hellwig	3235d 21h	/eco32/trunk/fpga/