OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] - Rev 331

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
331 machine monitor: init kbd and dsp only if explicitly requested hellwig 2846d 18h /eco32/trunk/monitor/monitor/boards/s3e-500/
242 monitor for Digilent board honors console I/O switch setting hellwig 3560d 14h /eco32/trunk/monitor/monitor/boards/s3e-500/
201 steps toward a debugging monitor hellwig 3587d 02h /eco32/trunk/monitor/monitor/boards/s3e-500/
200 steps toward a debugging monitor hellwig 3587d 19h /eco32/trunk/monitor/monitor/boards/s3e-500/
185 monitor jump vector updated hellwig 3598d 01h /eco32/trunk/monitor/monitor/boards/s3e-500/
184 init routine for disk over serial line hellwig 3599d 01h /eco32/trunk/monitor/monitor/boards/s3e-500/
182 monitor, several changes hellwig 3599d 05h /eco32/trunk/monitor/monitor/boards/s3e-500/
180 monitor recognizes BadAccess register hellwig 3603d 04h /eco32/trunk/monitor/monitor/boards/s3e-500/
84 monitor: bad address register added hellwig 3772d 05h /eco32/trunk/monitor/monitor/boards/s3e-500/
64 monitors re-organized hellwig 3779d 02h /eco32/trunk/monitor/monitor/boards/s3e-500/
63 monitors re-organized hellwig 3779d 02h /eco32/trunk/monitor/monitor/boards/s3e-500/
61 monitors re-organized hellwig 3779d 03h /eco32/trunk/monitor/monitor/boards/digilent/
60 monitors re-organized hellwig 3779d 03h /eco32/trunk/monitor/monitor/boards/digilent/
58 monitors re-organized hellwig 3779d 03h /eco32/trunk/monitor/monitor/boards/digilent/
57 monitors re-organized hellwig 3779d 03h /digilent/
56 monitors re-organized hellwig 3779d 04h /digilent/
54 digilent monitor update hellwig 3779d 05h /digilent/
50 digilent monitor update hellwig 3779d 22h /digilent/
39 bin2exo tool updated hellwig 3780d 20h /digilent/
16 monitor added hellwig 3797d 00h /digilent/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.