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Rev Log message Author Age Path
315 Updated testbench. Some more testcases, some repaired. tadejm 7487d 08h /ethmac/branches/unneback/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7487d 08h /ethmac/branches/unneback/
311 Update script for running different file list files for different RAM models. tadejm 7487d 08h /ethmac/branches/unneback/
310 More signals. tadejm 7487d 08h /ethmac/branches/unneback/
309 Update file list files for different RAM models with byte select accessing. tadejm 7487d 08h /ethmac/branches/unneback/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7487d 08h /ethmac/branches/unneback/
306 Lapsus fixed (!we -> ~we). simons 7488d 06h /ethmac/branches/unneback/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7510d 02h /ethmac/branches/unneback/
302 mbist signals updated according to newest convention markom 7536d 13h /ethmac/branches/unneback/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7547d 05h /ethmac/branches/unneback/
299 Artisan RAMs added. mohor 7594d 09h /ethmac/branches/unneback/
297 Artisan ram instance added. simons 7600d 04h /ethmac/branches/unneback/
295 Few minor changes. tadejm 7601d 07h /ethmac/branches/unneback/
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7603d 08h /ethmac/branches/unneback/
293 initial. tadejm 7627d 05h /ethmac/branches/unneback/
292 Corrected mistake. tadejm 7627d 05h /ethmac/branches/unneback/
291 initial tadejm 7627d 06h /ethmac/branches/unneback/
290 Additional checking for FAILED tests added - for ATS. tadejm 7627d 07h /ethmac/branches/unneback/
288 This file was not part of the RTL before, but it should be here. simons 7636d 06h /ethmac/branches/unneback/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7662d 09h /ethmac/branches/unneback/

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