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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 246

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Rev	Log message	Author	Age	Path
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8025d 10h	/ethmac/branches/unneback/rtl/verilog/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8026d 06h	/ethmac/branches/unneback/rtl/verilog/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	8027d 02h	/ethmac/branches/unneback/rtl/verilog/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	8027d 02h	/ethmac/branches/unneback/rtl/verilog/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	8027d 02h	/ethmac/branches/unneback/rtl/verilog/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	8027d 02h	/ethmac/branches/unneback/rtl/verilog/
238	Defines fixed to use generic RAM by default.	mohor	8039d 06h	/ethmac/branches/unneback/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	8041d 12h	/ethmac/branches/unneback/rtl/verilog/
232	fpga define added.	mohor	8047d 06h	/ethmac/branches/unneback/rtl/verilog/
229	case changed to casex.	mohor	8053d 04h	/ethmac/branches/unneback/rtl/verilog/
227	Changed BIST scan signals.	tadejm	8053d 08h	/ethmac/branches/unneback/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	8053d 09h	/ethmac/branches/unneback/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	8057d 08h	/ethmac/branches/unneback/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8060d 09h	/ethmac/branches/unneback/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	8060d 11h	/ethmac/branches/unneback/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	8061d 08h	/ethmac/branches/unneback/rtl/verilog/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8061d 08h	/ethmac/branches/unneback/rtl/verilog/
212	Minor $display change.	mohor	8061d 08h	/ethmac/branches/unneback/rtl/verilog/
211	Bist added.	mohor	8061d 08h	/ethmac/branches/unneback/rtl/verilog/
210	BIST added.	mohor	8061d 08h	/ethmac/branches/unneback/rtl/verilog/

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 246

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