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[/] [ethmac/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 93

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Rev	Log message	Author	Age	Path
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8124d 08h	/ethmac/tags/asyst_3/rtl/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8125d 11h	/ethmac/tags/asyst_3/rtl/verilog/
91	Comments in Slovene language removed.	mohor	8125d 11h	/ethmac/tags/asyst_3/rtl/verilog/
90	casex changed with case, fifo reset changed.	mohor	8125d 11h	/ethmac/tags/asyst_3/rtl/verilog/
88	rx_fifo was not always cleared ok. Fixed.	mohor	8135d 08h	/ethmac/tags/asyst_3/rtl/verilog/
87	Status was not latched correctly sometimes. Fixed.	mohor	8135d 10h	/ethmac/tags/asyst_3/rtl/verilog/
86	Big Endian problem when sending frames fixed.	mohor	8136d 17h	/ethmac/tags/asyst_3/rtl/verilog/
85	Log info was missing.	mohor	8142d 03h	/ethmac/tags/asyst_3/rtl/verilog/
84	LinkFail signal was not latching appropriate bit.	mohor	8142d 03h	/ethmac/tags/asyst_3/rtl/verilog/
83	MAC address recognition was not correct (bytes swaped).	mohor	8142d 03h	/ethmac/tags/asyst_3/rtl/verilog/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8142d 05h	/ethmac/tags/asyst_3/rtl/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
79	RetryCntLatched was unused and removed from design	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
78	WB_SEL_I was unused and removed from design	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
77	Interrupts changed	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
76	Interrupts changed in the top file	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
75	r_Bro is used for accepting/denying frames	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
74	Reset values are passed to registers through parameters	mohor	8146d 07h	/ethmac/tags/asyst_3/rtl/verilog/
73	Number of interrupts changed	mohor	8146d 08h	/ethmac/tags/asyst_3/rtl/verilog/
72	Retry is not activated when a Tx Underrun occured	mohor	8150d 11h	/ethmac/tags/asyst_3/rtl/verilog/

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[/] [ethmac/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 93

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