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[/] [ethmac/] [tags/] [rel_1/] [rtl/] - Rev 47

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Rev	Log message	Author	Age	Path
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8164d 18h	/ethmac/tags/rel_1/rtl/
46	HASH0 and HASH1 registers added.	mohor	8164d 18h	/ethmac/tags/rel_1/rtl/
43	Tx status is written back to the BD.	mohor	8166d 02h	/ethmac/tags/rel_1/rtl/
42	Rx status is written back to the BD.	mohor	8168d 19h	/ethmac/tags/rel_1/rtl/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8170d 21h	/ethmac/tags/rel_1/rtl/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8171d 18h	/ethmac/tags/rel_1/rtl/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8175d 22h	/ethmac/tags/rel_1/rtl/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8185d 00h	/ethmac/tags/rel_1/rtl/
37	Link in the header changed.	mohor	8185d 01h	/ethmac/tags/rel_1/rtl/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8233d 20h	/ethmac/tags/rel_1/rtl/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8234d 00h	/ethmac/tags/rel_1/rtl/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8234d 01h	/ethmac/tags/rel_1/rtl/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8255d 21h	/ethmac/tags/rel_1/rtl/
24	Log file added.	mohor	8281d 00h	/ethmac/tags/rel_1/rtl/
23	Number of addresses (wb_adr_i) minimized.	mohor	8281d 00h	/ethmac/tags/rel_1/rtl/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8281d 02h	/ethmac/tags/rel_1/rtl/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8281d 23h	/ethmac/tags/rel_1/rtl/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8305d 20h	/ethmac/tags/rel_1/rtl/
18	Few little NCSIM warnings fixed.	mohor	8318d 21h	/ethmac/tags/rel_1/rtl/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8345d 21h	/ethmac/tags/rel_1/rtl/

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[/] [ethmac/] [tags/] [rel_1/] [rtl/] - Rev 47

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