OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 55

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
55 Changed that were lost with last update put back to the file. mohor 8136d 09h /ethmac/tags/rel_12/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8137d 00h /ethmac/tags/rel_12/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8137d 00h /ethmac/tags/rel_12/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8137d 00h /ethmac/tags/rel_12/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8137d 01h /ethmac/tags/rel_12/rtl/verilog/
48 RxOverRun added to statuses. mohor 8139d 03h /ethmac/tags/rel_12/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8139d 03h /ethmac/tags/rel_12/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8139d 03h /ethmac/tags/rel_12/rtl/verilog/
43 Tx status is written back to the BD. mohor 8140d 11h /ethmac/tags/rel_12/rtl/verilog/
42 Rx status is written back to the BD. mohor 8143d 04h /ethmac/tags/rel_12/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8145d 06h /ethmac/tags/rel_12/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8146d 04h /ethmac/tags/rel_12/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8150d 08h /ethmac/tags/rel_12/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8159d 10h /ethmac/tags/rel_12/rtl/verilog/
37 Link in the header changed. mohor 8159d 10h /ethmac/tags/rel_12/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8208d 05h /ethmac/tags/rel_12/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8208d 10h /ethmac/tags/rel_12/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8208d 10h /ethmac/tags/rel_12/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8230d 06h /ethmac/tags/rel_12/rtl/verilog/
24 Log file added. mohor 8255d 09h /ethmac/tags/rel_12/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.