OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_13/] [rtl/] - Rev 221

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7906d 19h /ethmac/tags/rel_13/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7909d 20h /ethmac/tags/rel_13/rtl/
218 Typo error fixed. (When using Bist) mohor 7909d 22h /ethmac/tags/rel_13/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7910d 18h /ethmac/tags/rel_13/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7910d 18h /ethmac/tags/rel_13/rtl/
212 Minor $display change. mohor 7910d 18h /ethmac/tags/rel_13/rtl/
211 Bist added. mohor 7910d 19h /ethmac/tags/rel_13/rtl/
210 BIST added. mohor 7910d 19h /ethmac/tags/rel_13/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7927d 17h /ethmac/tags/rel_13/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7927d 17h /ethmac/tags/rel_13/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7930d 18h /ethmac/tags/rel_13/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7938d 20h /ethmac/tags/rel_13/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7939d 21h /ethmac/tags/rel_13/rtl/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7940d 21h /ethmac/tags/rel_13/rtl/
165 HASH improvement needed. mohor 7941d 01h /ethmac/tags/rel_13/rtl/
164 Ethernet debug registers removed. mohor 7941d 01h /ethmac/tags/rel_13/rtl/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7941d 22h /ethmac/tags/rel_13/rtl/
160 error acknowledge cycle termination added to display. mohor 7941d 22h /ethmac/tags/rel_13/rtl/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7942d 19h /ethmac/tags/rel_13/rtl/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7946d 16h /ethmac/tags/rel_13/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.