OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 29

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
29 Generic memory model is used. Defines are changed for the same reason. mohor 8271d 13h /ethmac/tags/rel_14/rtl/verilog/
24 Log file added. mohor 8296d 15h /ethmac/tags/rel_14/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8296d 16h /ethmac/tags/rel_14/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8296d 18h /ethmac/tags/rel_14/rtl/verilog/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8297d 15h /ethmac/tags/rel_14/rtl/verilog/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8321d 12h /ethmac/tags/rel_14/rtl/verilog/
18 Few little NCSIM warnings fixed. mohor 8334d 13h /ethmac/tags/rel_14/rtl/verilog/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8361d 13h /ethmac/tags/rel_14/rtl/verilog/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8368d 19h /ethmac/tags/rel_14/rtl/verilog/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8370d 12h /ethmac/tags/rel_14/rtl/verilog/
14 Unconnected signals are now connected. mohor 8374d 18h /ethmac/tags/rel_14/rtl/verilog/
10 Directory structure changed. Files checked and joind together. mohor 8377d 06h /ethmac/tags/rel_14/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.