OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_16/] [rtl/] [verilog/] - Rev 83

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
83 MAC address recognition was not correct (bytes swaped). mohor 8184d 19h /ethmac/tags/rel_16/rtl/verilog/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8184d 21h /ethmac/tags/rel_16/rtl/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
79 RetryCntLatched was unused and removed from design mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
78 WB_SEL_I was unused and removed from design mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
77 Interrupts changed mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
76 Interrupts changed in the top file mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
74 Reset values are passed to registers through parameters mohor 8188d 23h /ethmac/tags/rel_16/rtl/verilog/
73 Number of interrupts changed mohor 8189d 00h /ethmac/tags/rel_16/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 8193d 03h /ethmac/tags/rel_16/rtl/verilog/
70 Small fixes. mohor 8197d 05h /ethmac/tags/rel_16/rtl/verilog/
69 Define missmatch fixed. mohor 8198d 02h /ethmac/tags/rel_16/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 8199d 02h /ethmac/tags/rel_16/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8199d 03h /ethmac/tags/rel_16/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 8199d 08h /ethmac/tags/rel_16/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8199d 23h /ethmac/tags/rel_16/rtl/verilog/
63 RxAbort is connected differently. mohor 8200d 02h /ethmac/tags/rel_16/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 8200d 02h /ethmac/tags/rel_16/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 8200d 03h /ethmac/tags/rel_16/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.