OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/
58 File format changed. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/
57 Format of the file changed a bit. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/
56 File format fixed a bit. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8146d 18h /ethmac/tags/rel_17/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8146d 18h /ethmac/tags/rel_17/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8146d 18h /ethmac/tags/rel_17/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8146d 19h /ethmac/tags/rel_17/rtl/verilog/
48 RxOverRun added to statuses. mohor 8148d 21h /ethmac/tags/rel_17/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8148d 21h /ethmac/tags/rel_17/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8148d 21h /ethmac/tags/rel_17/rtl/verilog/
43 Tx status is written back to the BD. mohor 8150d 05h /ethmac/tags/rel_17/rtl/verilog/
42 Rx status is written back to the BD. mohor 8152d 22h /ethmac/tags/rel_17/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8155d 00h /ethmac/tags/rel_17/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8155d 22h /ethmac/tags/rel_17/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8160d 02h /ethmac/tags/rel_17/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8169d 04h /ethmac/tags/rel_17/rtl/verilog/
37 Link in the header changed. mohor 8169d 04h /ethmac/tags/rel_17/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8217d 23h /ethmac/tags/rel_17/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.