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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 96

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Rev	Log message	Author	Age	Path
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8106d 23h	/ethmac/tags/rel_17/rtl/verilog/
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8107d 01h	/ethmac/tags/rel_17/rtl/verilog/
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8107d 01h	/ethmac/tags/rel_17/rtl/verilog/
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8112d 00h	/ethmac/tags/rel_17/rtl/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8113d 02h	/ethmac/tags/rel_17/rtl/verilog/
91	Comments in Slovene language removed.	mohor	8113d 02h	/ethmac/tags/rel_17/rtl/verilog/
90	casex changed with case, fifo reset changed.	mohor	8113d 02h	/ethmac/tags/rel_17/rtl/verilog/
88	rx_fifo was not always cleared ok. Fixed.	mohor	8122d 23h	/ethmac/tags/rel_17/rtl/verilog/
87	Status was not latched correctly sometimes. Fixed.	mohor	8123d 01h	/ethmac/tags/rel_17/rtl/verilog/
86	Big Endian problem when sending frames fixed.	mohor	8124d 08h	/ethmac/tags/rel_17/rtl/verilog/
85	Log info was missing.	mohor	8129d 18h	/ethmac/tags/rel_17/rtl/verilog/
84	LinkFail signal was not latching appropriate bit.	mohor	8129d 18h	/ethmac/tags/rel_17/rtl/verilog/
83	MAC address recognition was not correct (bytes swaped).	mohor	8129d 18h	/ethmac/tags/rel_17/rtl/verilog/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8129d 20h	/ethmac/tags/rel_17/rtl/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8133d 22h	/ethmac/tags/rel_17/rtl/verilog/
79	RetryCntLatched was unused and removed from design	mohor	8133d 23h	/ethmac/tags/rel_17/rtl/verilog/
78	WB_SEL_I was unused and removed from design	mohor	8133d 23h	/ethmac/tags/rel_17/rtl/verilog/
77	Interrupts changed	mohor	8133d 23h	/ethmac/tags/rel_17/rtl/verilog/
76	Interrupts changed in the top file	mohor	8133d 23h	/ethmac/tags/rel_17/rtl/verilog/
75	r_Bro is used for accepting/denying frames	mohor	8133d 23h	/ethmac/tags/rel_17/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 96

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