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[/] [ethmac/] [tags/] [rel_18/] - Rev 115

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Rev	Log message	Author	Age	Path
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7991d 01h	/ethmac/tags/rel_18/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7991d 22h	/ethmac/tags/rel_18/
113	RxPointer bug fixed.	mohor	7998d 14h	/ethmac/tags/rel_18/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7999d 04h	/ethmac/tags/rel_18/
111	Master state machine had a bug when switching from master write to master read.	mohor	7999d 17h	/ethmac/tags/rel_18/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7999d 20h	/ethmac/tags/rel_18/
109	Comment removed.	mohor	7999d 21h	/ethmac/tags/rel_18/
108	Testbench supports unaligned accesses.	mohor	8067d 07h	/ethmac/tags/rel_18/
107	TX_BUF_BASE changed.	mohor	8067d 07h	/ethmac/tags/rel_18/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8067d 07h	/ethmac/tags/rel_18/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8076d 08h	/ethmac/tags/rel_18/
104	FCS should not be included in NibbleMinFl.	mohor	8078d 02h	/ethmac/tags/rel_18/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8078d 03h	/ethmac/tags/rel_18/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8078d 03h	/ethmac/tags/rel_18/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8078d 03h	/ethmac/tags/rel_18/
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8078d 03h	/ethmac/tags/rel_18/
99	Document revised.	mohor	8085d 02h	/ethmac/tags/rel_18/
98	Document revised.	mohor	8085d 02h	/ethmac/tags/rel_18/
97	Small typo fixed.	lampret	8102d 01h	/ethmac/tags/rel_18/
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8106d 01h	/ethmac/tags/rel_18/

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Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_18/] - Rev 115

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