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Rev Log message Author Age Path
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7989d 19h /ethmac/tags/rel_22/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8066d 22h /ethmac/tags/rel_22/bench/verilog/
107 TX_BUF_BASE changed. mohor 8066d 22h /ethmac/tags/rel_22/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8111d 20h /ethmac/tags/rel_22/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8132d 16h /ethmac/tags/rel_22/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8142d 20h /ethmac/tags/rel_22/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 8143d 01h /ethmac/tags/rel_22/bench/verilog/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8144d 13h /ethmac/tags/rel_22/bench/verilog/
49 HASH0 and HASH1 register read/write added. mohor 8146d 12h /ethmac/tags/rel_22/bench/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8152d 19h /ethmac/tags/rel_22/bench/verilog/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8212d 20h /ethmac/tags/rel_22/bench/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8262d 21h /ethmac/tags/rel_22/bench/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8263d 00h /ethmac/tags/rel_22/bench/verilog/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8287d 18h /ethmac/tags/rel_22/bench/verilog/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8327d 19h /ethmac/tags/rel_22/bench/verilog/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8336d 18h /ethmac/tags/rel_22/bench/verilog/
12 Directory structure changed. Files checked and joind together. mohor 8343d 11h /ethmac/tags/rel_22/bench/verilog/

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