OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_25/] [bench/] [verilog/] - Rev 274

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
274 Backup version. Not fully working. tadejm 7821d 03h /ethmac/tags/rel_25/bench/verilog/
267 Full duplex control frames tested. mohor 7877d 07h /ethmac/tags/rel_25/bench/verilog/
266 Flow control test almost finished. mohor 7882d 06h /ethmac/tags/rel_25/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7882d 21h /ethmac/tags/rel_25/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7883d 09h /ethmac/tags/rel_25/bench/verilog/
254 Temp version. mohor 7885d 03h /ethmac/tags/rel_25/bench/verilog/
252 Just some updates. tadejm 7885d 05h /ethmac/tags/rel_25/bench/verilog/
243 Late collision is not reported any more. tadejm 7890d 10h /ethmac/tags/rel_25/bench/verilog/
227 Changed BIST scan signals. tadejm 7917d 06h /ethmac/tags/rel_25/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7917d 09h /ethmac/tags/rel_25/bench/verilog/
216 Bist signals added. mohor 7924d 10h /ethmac/tags/rel_25/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7926d 10h /ethmac/tags/rel_25/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7945d 09h /ethmac/tags/rel_25/bench/verilog/
192 Some additional reports added tadej 7947d 05h /ethmac/tags/rel_25/bench/verilog/
191 Bug repaired in eth_phy device tadej 7947d 05h /ethmac/tags/rel_25/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7947d 06h /ethmac/tags/rel_25/bench/verilog/
188 PHY changed. tadej 7948d 03h /ethmac/tags/rel_25/bench/verilog/
182 Full duplex test improved. tadej 7949d 05h /ethmac/tags/rel_25/bench/verilog/
181 MIIM test look better. mohor 7949d 08h /ethmac/tags/rel_25/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7952d 04h /ethmac/tags/rel_25/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.