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[/] [ethmac/] [tags/] [rel_25/] [bench/] [verilog/] - Rev 299

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Rev Log message Author Age Path
299 Artisan RAMs added. mohor 7650d 18h /ethmac/tags/rel_25/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7718d 19h /ethmac/tags/rel_25/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7851d 15h /ethmac/tags/rel_25/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7852d 17h /ethmac/tags/rel_25/bench/verilog/
274 Backup version. Not fully working. tadejm 7860d 11h /ethmac/tags/rel_25/bench/verilog/
267 Full duplex control frames tested. mohor 7916d 14h /ethmac/tags/rel_25/bench/verilog/
266 Flow control test almost finished. mohor 7921d 13h /ethmac/tags/rel_25/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7922d 04h /ethmac/tags/rel_25/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7922d 17h /ethmac/tags/rel_25/bench/verilog/
254 Temp version. mohor 7924d 10h /ethmac/tags/rel_25/bench/verilog/
252 Just some updates. tadejm 7924d 13h /ethmac/tags/rel_25/bench/verilog/
243 Late collision is not reported any more. tadejm 7929d 17h /ethmac/tags/rel_25/bench/verilog/
227 Changed BIST scan signals. tadejm 7956d 14h /ethmac/tags/rel_25/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7956d 17h /ethmac/tags/rel_25/bench/verilog/
216 Bist signals added. mohor 7963d 17h /ethmac/tags/rel_25/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7965d 17h /ethmac/tags/rel_25/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7984d 16h /ethmac/tags/rel_25/bench/verilog/
192 Some additional reports added tadej 7986d 13h /ethmac/tags/rel_25/bench/verilog/
191 Bug repaired in eth_phy device tadej 7986d 13h /ethmac/tags/rel_25/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7986d 14h /ethmac/tags/rel_25/bench/verilog/

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