OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_4/] [rtl/] [verilog/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 Reset values are passed to registers through parameters mohor 8164d 07h /ethmac/tags/rel_4/rtl/verilog/
73 Number of interrupts changed mohor 8164d 07h /ethmac/tags/rel_4/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 8168d 10h /ethmac/tags/rel_4/rtl/verilog/
70 Small fixes. mohor 8172d 12h /ethmac/tags/rel_4/rtl/verilog/
69 Define missmatch fixed. mohor 8173d 09h /ethmac/tags/rel_4/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 8174d 09h /ethmac/tags/rel_4/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8174d 10h /ethmac/tags/rel_4/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 8174d 16h /ethmac/tags/rel_4/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8175d 06h /ethmac/tags/rel_4/rtl/verilog/
63 RxAbort is connected differently. mohor 8175d 09h /ethmac/tags/rel_4/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 8175d 09h /ethmac/tags/rel_4/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 8175d 11h /ethmac/tags/rel_4/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8175d 11h /ethmac/tags/rel_4/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8175d 11h /ethmac/tags/rel_4/rtl/verilog/
58 File format changed. mohor 8175d 12h /ethmac/tags/rel_4/rtl/verilog/
57 Format of the file changed a bit. mohor 8175d 12h /ethmac/tags/rel_4/rtl/verilog/
56 File format fixed a bit. mohor 8175d 12h /ethmac/tags/rel_4/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 8175d 12h /ethmac/tags/rel_4/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8176d 02h /ethmac/tags/rel_4/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8176d 02h /ethmac/tags/rel_4/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.