URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] - Rev 317

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Rev	Log message	Author	Age	Path
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7373d 04h	/ethmac/trunk/
315	Updated testbench. Some more testcases, some repaired.	tadejm	7476d 00h	/ethmac/trunk/
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7476d 00h	/ethmac/trunk/
311	Update script for running different file list files for different RAM models.	tadejm	7476d 01h	/ethmac/trunk/
310	More signals.	tadejm	7476d 01h	/ethmac/trunk/
309	Update file list files for different RAM models with byte select accessing.	tadejm	7476d 01h	/ethmac/trunk/
308	Moved RAM model file path from sim_file_list.lst to this file.	tadejm	7476d 01h	/ethmac/trunk/
306	Lapsus fixed (!we -> ~we).	simons	7476d 22h	/ethmac/trunk/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7498d 19h	/ethmac/trunk/
302	mbist signals updated according to newest convention	markom	7525d 05h	/ethmac/trunk/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7535d 21h	/ethmac/trunk/
299	Artisan RAMs added.	mohor	7583d 01h	/ethmac/trunk/
297	Artisan ram instance added.	simons	7588d 20h	/ethmac/trunk/
295	Few minor changes.	tadejm	7590d 00h	/ethmac/trunk/
294	Added path to a file with distributed RAM instances for xilinx.	tadejm	7592d 00h	/ethmac/trunk/
293	initial.	tadejm	7615d 21h	/ethmac/trunk/
292	Corrected mistake.	tadejm	7615d 21h	/ethmac/trunk/
291	initial	tadejm	7615d 22h	/ethmac/trunk/
290	Additional checking for FAILED tests added - for ATS.	tadejm	7615d 23h	/ethmac/trunk/
288	This file was not part of the RTL before, but it should be here.	simons	7624d 22h	/ethmac/trunk/

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[/] [ethmac/] [trunk/] - Rev 317

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