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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 364

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Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4882d 15h /ethmac/trunk/bench/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4887d 17h /ethmac/trunk/bench/verilog/
348 Added option to dump VCD files olof 4904d 16h /ethmac/trunk/bench/verilog/
346 Updated project location olof 4904d 19h /ethmac/trunk/bench/verilog/
345 Temporarily disable failing tests olof 4904d 20h /ethmac/trunk/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4910d 22h /ethmac/trunk/bench/verilog/
343 Address miss should not be asserted on short frames olof 4914d 18h /ethmac/trunk/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4914d 18h /ethmac/trunk/bench/verilog/
338 root 5708d 21h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5766d 02h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 7214d 04h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7242d 23h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7574d 20h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7686d 23h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7736d 04h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7794d 00h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7862d 00h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7994d 20h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7995d 23h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 8003d 17h /ethmac/trunk/bench/verilog/

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