URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 301

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7704d 18h	/ethmac/trunk/rtl/verilog/
297	Artisan ram instance added.	simons	7757d 17h	/ethmac/trunk/rtl/verilog/
288	This file was not part of the RTL before, but it should be here.	simons	7793d 19h	/ethmac/trunk/rtl/verilog/
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7819d 22h	/ethmac/trunk/rtl/verilog/
285	Binary operator used instead of unary (xnor).	mohor	7819d 23h	/ethmac/trunk/rtl/verilog/
284	Busy was set 2 cycles too late. Reported by Dennis Scott.	mohor	7848d 00h	/ethmac/trunk/rtl/verilog/
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7875d 18h	/ethmac/trunk/rtl/verilog/
280	Reset has priority in some flipflops.	mohor	7953d 19h	/ethmac/trunk/rtl/verilog/
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7953d 20h	/ethmac/trunk/rtl/verilog/
277	When padding was enabled and crc disabled, frame was not ended correctly.	mohor	7953d 20h	/ethmac/trunk/rtl/verilog/
276	Defer indication changed.	tadejm	7953d 21h	/ethmac/trunk/rtl/verilog/
275	Fix MTxErr or prevent sending too big frames.	mohor	7961d 01h	/ethmac/trunk/rtl/verilog/
272	When control packets were received, they were ignored in some cases.	tadejm	7961d 20h	/ethmac/trunk/rtl/verilog/
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7962d 22h	/ethmac/trunk/rtl/verilog/
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7963d 22h	/ethmac/trunk/rtl/verilog/
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	8022d 21h	/ethmac/trunk/rtl/verilog/
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8023d 08h	/ethmac/trunk/rtl/verilog/
259	In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of additional logic is necessery (FIFO for looping the data).	mohor	8024d 09h	/ethmac/trunk/rtl/verilog/
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	8024d 10h	/ethmac/trunk/rtl/verilog/
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	8024d 10h	/ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 301

Filtering Options