OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 367

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4568d 20h /ethmac/trunk/rtl/verilog/
366 Readded eth_top.v with a deprecation warning olof 4693d 00h /ethmac/trunk/rtl/verilog/
365 Whitespace cleanup olof 4693d 23h /ethmac/trunk/rtl/verilog/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4694d 21h /ethmac/trunk/rtl/verilog/
360 Added partial implementation of the debug register from ORPSoC olof 4696d 04h /ethmac/trunk/rtl/verilog/
359 Verilator linting fixes olof 4698d 07h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4699d 21h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4699d 21h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4699d 23h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4699d 23h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4700d 00h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4702d 01h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4706d 07h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4714d 21h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4714d 22h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4715d 22h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4717d 00h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4727d 00h /ethmac/trunk/rtl/verilog/
338 root 5521d 02h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5578d 07h /ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.