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[/] [ethmac10g/] [tags/] [V10/] - Rev 28

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Rev Log message Author Age Path
28 First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST. mvpratt 6728d 05h /ethmac10g/tags/V10/
27 xilinx coregen fisher5090 6738d 10h /ethmac10g/tags/V10/
26 good edition fisher5090 6738d 10h /ethmac10g/tags/V10/
25 no message fisher5090 6738d 10h /ethmac10g/tags/V10/
24 First cut. One of the main culprits for the timing violations. godzilla 6741d 01h /ethmac10g/tags/V10/
23 First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations. godzilla 6741d 01h /ethmac10g/tags/V10/
22 First cut. Original code from Easic but add some extra controls. godzilla 6741d 01h /ethmac10g/tags/V10/
21 First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats.
So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.		 godzilla 6741d 01h /ethmac10g/tags/V10/
20 First cut. Still need to update the document with design changes. godzilla 6741d 02h /ethmac10g/tags/V10/
19 First cut. godzilla 6741d 02h /ethmac10g/tags/V10/
18 works well fisher5090 6745d 15h /ethmac10g/tags/V10/
17 crc test fisher5090 6745d 21h /ethmac10g/tags/V10/
16 use counter fisher5090 6749d 06h /ethmac10g/tags/V10/
15 crc module fisher5090 6749d 06h /ethmac10g/tags/V10/
14 no more used fisher5090 6749d 06h /ethmac10g/tags/V10/
13 first commit. not yet ready to compile mvpratt 6749d 06h /ethmac10g/tags/V10/
12 200MHZ fisher5090 6750d 15h /ethmac10g/tags/V10/
11 200MHZ fisher5090 6750d 15h /ethmac10g/tags/V10/
10 200MHZ fisher5090 6750d 15h /ethmac10g/tags/V10/
9 with max frequence of 200MHZ fisher5090 6756d 10h /ethmac10g/tags/V10/

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