URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

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[/] [ethmac10g/] [tags/] [V10/] - Rev 35

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Rev	Log message	Author	Age	Path
35	no message	godzilla	6669d 16h	/ethmac10g/tags/V10/
34	Rewritten code.	godzilla	6669d 16h	/ethmac10g/tags/V10/
33	Rewritten code.	godzilla	6669d 17h	/ethmac10g/tags/V10/
32	no message	fisher5090	6687d 01h	/ethmac10g/tags/V10/
31	no message	fisher5090	6687d 01h	/ethmac10g/tags/V10/
30	no message	fisher5090	6715d 00h	/ethmac10g/tags/V10/
29	no message	fisher5090	6715d 09h	/ethmac10g/tags/V10/
28	First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST.	mvpratt	6717d 19h	/ethmac10g/tags/V10/
27	xilinx coregen	fisher5090	6728d 00h	/ethmac10g/tags/V10/
26	good edition	fisher5090	6728d 00h	/ethmac10g/tags/V10/
25	no message	fisher5090	6728d 00h	/ethmac10g/tags/V10/
24	First cut. One of the main culprits for the timing violations.	godzilla	6730d 16h	/ethmac10g/tags/V10/
23	First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations.	godzilla	6730d 16h	/ethmac10g/tags/V10/
22	First cut. Original code from Easic but add some extra controls.	godzilla	6730d 16h	/ethmac10g/tags/V10/
21	First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats. So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.	godzilla	6730d 16h	/ethmac10g/tags/V10/
20	First cut. Still need to update the document with design changes.	godzilla	6730d 16h	/ethmac10g/tags/V10/
19	First cut.	godzilla	6730d 16h	/ethmac10g/tags/V10/
18	works well	fisher5090	6735d 05h	/ethmac10g/tags/V10/
17	crc test	fisher5090	6735d 12h	/ethmac10g/tags/V10/
16	use counter	fisher5090	6738d 21h	/ethmac10g/tags/V10/

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Subversion Repositories ethmac10g

[/] [ethmac10g/] [tags/] [V10/] - Rev 35

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