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[/] [ethmac10g/] [trunk/] - Rev 37

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Rev Log message Author Age Path
37 no message fisher5090 6646d 02h /ethmac10g/trunk/
36 no message godzilla 6709d 10h /ethmac10g/trunk/
35 no message godzilla 6712d 10h /ethmac10g/trunk/
34 Rewritten code. godzilla 6712d 10h /ethmac10g/trunk/
33 Rewritten code. godzilla 6712d 10h /ethmac10g/trunk/
32 no message fisher5090 6729d 18h /ethmac10g/trunk/
31 no message fisher5090 6729d 18h /ethmac10g/trunk/
30 no message fisher5090 6757d 17h /ethmac10g/trunk/
29 no message fisher5090 6758d 02h /ethmac10g/trunk/
28 First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST. mvpratt 6760d 13h /ethmac10g/trunk/
27 xilinx coregen fisher5090 6770d 17h /ethmac10g/trunk/
26 good edition fisher5090 6770d 18h /ethmac10g/trunk/
25 no message fisher5090 6770d 18h /ethmac10g/trunk/
24 First cut. One of the main culprits for the timing violations. godzilla 6773d 09h /ethmac10g/trunk/
23 First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations. godzilla 6773d 09h /ethmac10g/trunk/
22 First cut. Original code from Easic but add some extra controls. godzilla 6773d 09h /ethmac10g/trunk/
21 First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats.
So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.		 godzilla 6773d 09h /ethmac10g/trunk/
20 First cut. Still need to update the document with design changes. godzilla 6773d 09h /ethmac10g/trunk/
19 First cut. godzilla 6773d 09h /ethmac10g/trunk/
18 works well fisher5090 6777d 22h /ethmac10g/trunk/

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