URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] - Rev 72

Rev	Log message	Author	Age	Path
72	New directory structure.	root	5566d 01h	/ethmac10g/trunk/rtl/verilog/
71	Replay xilinx fifo with private fifo	fisher5090	5899d 21h	/ethmac10g/trunk/rtl/verilog/
70	no message	fisher5090	6563d 15h	/ethmac10g/trunk/rtl/verilog/
69	no message	fisher5090	6563d 16h	/ethmac10g/trunk/rtl/verilog/
67	modify mgmt_miim_rdy timing sequence	fisher5090	6564d 10h	/ethmac10g/trunk/rtl/verilog/
66	comments added	fisher5090	6564d 14h	/ethmac10g/trunk/rtl/verilog/
65	bad coding style, but works, will be modified later	fisher5090	6564d 17h	/ethmac10g/trunk/rtl/verilog/
64	no message	fisher5090	6567d 03h	/ethmac10g/trunk/rtl/verilog/
63	remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation	fisher5090	6567d 03h	/ethmac10g/trunk/rtl/verilog/
60	change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk	fisher5090	6567d 12h	/ethmac10g/trunk/rtl/verilog/
59	first version	fisher5090	6567d 13h	/ethmac10g/trunk/rtl/verilog/
57	both inband fcs and no inband fcs are OK	fisher5090	6567d 18h	/ethmac10g/trunk/rtl/verilog/
56	no message	fisher5090	6568d 10h	/ethmac10g/trunk/rtl/verilog/
52	modified the rx_good_frame and rx_bad_frame timing sequence	fisher5090	6568d 14h	/ethmac10g/trunk/rtl/verilog/
51	modified	fisher5090	6570d 18h	/ethmac10g/trunk/rtl/verilog/
50	good version	fisher5090	6570d 18h	/ethmac10g/trunk/rtl/verilog/
41	no message	fisher5090	6573d 17h	/ethmac10g/trunk/rtl/verilog/
39	first version	fisher5090	6579d 16h	/ethmac10g/trunk/rtl/verilog/