URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] - Rev 72

Rev	Log message	Author	Age	Path
72	New directory structure.	root	5603d 17h	/ethmac10g/trunk/rtl/verilog/rx_engine/
71	Replay xilinx fifo with private fifo	fisher5090	5937d 13h	/ethmac10g/trunk/rtl/verilog/rx_engine/
70	no message	fisher5090	6601d 07h	/ethmac10g/trunk/rtl/verilog/rx_engine/
69	no message	fisher5090	6601d 07h	/ethmac10g/trunk/rtl/verilog/rx_engine/
64	no message	fisher5090	6604d 19h	/ethmac10g/trunk/rtl/verilog/rx_engine/
63	remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation	fisher5090	6604d 19h	/ethmac10g/trunk/rtl/verilog/rx_engine/
60	change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk	fisher5090	6605d 04h	/ethmac10g/trunk/rtl/verilog/rx_engine/
57	both inband fcs and no inband fcs are OK	fisher5090	6605d 10h	/ethmac10g/trunk/rtl/verilog/rx_engine/
56	no message	fisher5090	6606d 02h	/ethmac10g/trunk/rtl/verilog/rx_engine/
52	modified the rx_good_frame and rx_bad_frame timing sequence	fisher5090	6606d 06h	/ethmac10g/trunk/rtl/verilog/rx_engine/
41	no message	fisher5090	6611d 09h	/ethmac10g/trunk/rtl/verilog/rx_engine/
39	first version	fisher5090	6617d 08h	/ethmac10g/trunk/rtl/verilog/rx_engine/