| Rev |
Log message |
Author |
Age |
Path |
| 45 |
Corrected erroneous assignment of "dbg" signal. |
wzab |
2692d 21h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/ |
| 44 |
Changed design for Kintex 7 based boards (AFCK, KC705) so that
they use the VEXTPROJ environment for VCS friendly project management
(described in http://doi.org/10.1117/12.2247944 ) |
wzab |
2692d 21h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/ |
| 43 |
Removed latch on "dbg" signal |
wzab |
2692d 22h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/ |
| 42 |
KC705 design upgraded to Vivado 2016.4
Corrrected indentation in a few files in AFCK design |
wzab |
2693d 02h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/ |
| 41 |
The AFCK project upgraded to Vivado 2016.4 |
wzab |
2693d 03h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/ |
| 40 |
The "jumbo frame version" renamed from "experimental" to "stable". |
wzab |
2693d 08h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/ |
| 38 |
In synthesis scripts added waiting, until bitsream is generated... |
wzab |
3293d 06h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 37 |
Added new design for AFCK board, which uses 8 10 Gbps links.
Additionally added I2C control of the AFCK Si57x based clock.
The I2C controller is driven via VIO blocks controlled by JTAG
interface from Vivado Tcl console.
Tcl scripts are in the fpga/src/AFCK/i2c_tools directory.
To configure clock to 156.25MHz, and to route it to links,
change directory to fpga/src/AFCK/i2c_tools and do
"source start_10g_links.tcl".
After the clock is reprogrammed, reconfigure the FPGA again
(it seems, that there is a problem with reseting links after
clock is reconfigured). |
wzab |
3294d 21h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 36 |
Added signals needed to ensure, that Si570/1 chip generates the clock.
Added signals driving the rate select lines in the SFP+ modules high.
Added two XDC files - the first one for FM-S14 in the FMC1
connector, the second one for FM-S14 in the FMC2 connector. |
wzab |
3310d 23h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 35 |
Changed comment in definition of the descriptor record
Updated IP cores in project for KC705 (to Vivado 2014.4) |
wzab |
3413d 23h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 33 |
Added script for automatic compilation of FADE for AFCK, using Vivado 2014.4 |
wzab |
3430d 09h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 32 |
Added the 4-channel FADE test implementation for the AFCK board. |
wzab |
3430d 13h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 27 |
Added file fade_one_channel, allowing to implement multiple FADE instances in a single FPGA. |
wzab |
3458d 11h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 26 |
Corrected small bug in CRC update in eth_sender8,vhd
Added counter of retransmitted packets.
Some minor changes in delay update parameters. |
wzab |
3492d 21h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 25 |
Modified the Tcl script for KC705 so, that it automatically runs synthesis, implementation and generates bitstream. |
wzab |
3516d 12h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 24 |
Added build scripts for KC705 (somehow they got omitted in version 22) |
wzab |
3517d 00h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 23 |
Added script allowing for batch compilation of FADE 10G for Atlys.
Just run build_proj_atlys.sh
Removed compilation of receiver2.c (which has been deleted) in the Makefile.
Slightly changed order of operation in the receiver2t.c |
wzab |
3517d 01h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 22 |
Sources reorganized so, that each ".xci" is in a separate directory.
Added script for rebuilding of Vivado project for KC705.
Just run the build_proj_kc705 script, and the project
will be created as kc705_10g3.xpr in the kc705_10g3 drirectory.
You can open it later on in Vivado 2014.3 and build the bitstream. |
wzab |
3517d 02h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 21 |
Changed the top entity for KC705, so that the FADE core is correctly reset
by the RESETMAC command.
Changed sending of the FCMD_RESET command form driver to the FPGA (as it
is not confirmed - the reinitialized core can't confirm the command).
Changed the receiver2t demo program so that it sends RESETMAC three times
before the transmission is started.
In the future, probably there should be a STATUS ioctl, which would
verify, that the core has been reset by RESETMAC.
Then the program should send RESETMAC, and afterwards read the STATUS,
verifying, that RESETMAC arrived FPGA. If not it should repeat the
above procedure (not implemented yet). |
wzab |
3517d 08h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
| 20 |
Cured problem with dta_eod missed, when buffer was full at the moment
when dta_eod was asserted.
It caused the client program to hang, as no end of data was transmitted
and no new data arrived... |
wzab |
3517d 23h |
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/ |
