URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [AFCK/] - Rev 37

Rev	Log message	Author	Age	Path
37	Added new design for AFCK board, which uses 8 10 Gbps links. Additionally added I2C control of the AFCK Si57x based clock. The I2C controller is driven via VIO blocks controlled by JTAG interface from Vivado Tcl console. Tcl scripts are in the fpga/src/AFCK/i2c_tools directory. To configure clock to 156.25MHz, and to route it to links, change directory to fpga/src/AFCK/i2c_tools and do "source start_10g_links.tcl". After the clock is reprogrammed, reconfigure the FPGA again (it seems, that there is a problem with reseting links after clock is reconfigured).	wzab	3328d 23h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/
36	Added signals needed to ensure, that Si570/1 chip generates the clock. Added signals driving the rate select lines in the SFP+ modules high. Added two XDC files - the first one for FM-S14 in the FMC1 connector, the second one for FM-S14 in the FMC2 connector.	wzab	3345d 01h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/
33	Added script for automatic compilation of FADE for AFCK, using Vivado 2014.4	wzab	3464d 11h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/
32	Added the 4-channel FADE test implementation for the AFCK board.	wzab	3464d 15h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/