URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] - Rev 22

Rev	Log message	Author	Age	Path
22	- fused multiply add	robfinch	1850d 12h	/ft816float/trunk/rtl/verilog/
21	- trunc function	robfinch	1851d 00h	/ft816float/trunk/rtl/verilog/
20	- fix nan propagation	robfinch	1852d 07h	/ft816float/trunk/rtl/verilog/
19	- latency 10 addsub	robfinch	1852d 07h	/ft816float/trunk/rtl/verilog/
18	- sigmoid function	robfinch	1854d 01h	/ft816float/trunk/rtl/verilog/
16	- added reciprocal square root estimate	robfinch	1854d 01h	/ft816float/trunk/rtl/verilog/
15	- added reciprocal estimate	robfinch	1855d 13h	/ft816float/trunk/rtl/verilog/
14	- added Goldschmidt divider	robfinch	2094d 11h	/ft816float/trunk/rtl/verilog/
13	- fix sticky bit position	robfinch	2337d 13h	/ft816float/trunk/rtl/verilog/
12	- added square root	robfinch	2339d 03h	/ft816float/trunk/rtl/verilog/
11	- fix multiply NaN	robfinch	2341d 03h	/ft816float/trunk/rtl/verilog/
10	- fp updated - test benches and vectors	robfinch	2341d 14h	/ft816float/trunk/rtl/verilog/
9	- added sample FP unit	robfinch	2764d 14h	/ft816float/trunk/rtl/verilog/
8	Updated better support for 80 bit / 128 bit ops	robfinch	2764d 14h	/ft816float/trunk/rtl/verilog/
7	adding missing reduction or function	robfinch	2916d 00h	/ft816float/trunk/rtl/verilog/
6	added more fp ops	robfinch	3022d 06h	/ft816float/trunk/rtl/verilog/
5	added floattoint inttofloat	robfinch	3023d 22h	/ft816float/trunk/rtl/verilog/
3	FT816Float - initial zrchive	robfinch	3495d 07h	/ft816float/trunk/rtl/verilog/