URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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Rev	Log message	Author	Age	Path
90	- sin / cosine	robfinch	365d 17h	/ft816float/trunk/rtl/verilog2/
89	- fix compare in DFPTrunc96	robfinch	521d 04h	/ft816float/trunk/rtl/verilog2/
88	- DPFTrunc() function	robfinch	521d 08h	/ft816float/trunk/rtl/verilog2/
86	- improve divider *10	robfinch	536d 10h	/ft816float/trunk/rtl/verilog2/
85	- improve divider *10	robfinch	536d 10h	/ft816float/trunk/rtl/verilog2/
84	- improve DPD divider	robfinch	536d 13h	/ft816float/trunk/rtl/verilog2/
83	- sign of zero is positive	robfinch	536d 16h	/ft816float/trunk/rtl/verilog2/
82	- improved divider	robfinch	536d 16h	/ft816float/trunk/rtl/verilog2/
81	- timing delay on divide - change adder in multiply	robfinch	537d 02h	/ft816float/trunk/rtl/verilog2/
80	- improve decimal float divide	robfinch	537d 07h	/ft816float/trunk/rtl/verilog2/
79	- fix sticky infinity	robfinch	538d 15h	/ft816float/trunk/rtl/verilog2/
78	- BCD subtraction - scaleb function	robfinch	539d 03h	/ft816float/trunk/rtl/verilog2/
76	- adjust 9 to 7	robfinch	541d 03h	/ft816float/trunk/rtl/verilog2/
75	- add triple precision decimal float	robfinch	541d 08h	/ft816float/trunk/rtl/verilog2/
74	- added single precision combo logic only version of FMA	robfinch	649d 02h	/ft816float/trunk/rtl/verilog2/
73	- fix Karatsuba carry chain bug	robfinch	820d 02h	/ft816float/trunk/rtl/verilog2/
72	- fix: mult32x32 prod high order bits	robfinch	820d 04h	/ft816float/trunk/rtl/verilog2/
71	- added decimal float reciprocal estimate	robfinch	828d 01h	/ft816float/trunk/rtl/verilog2/
70	- fix carry out for BCD add / sub	robfinch	828d 08h	/ft816float/trunk/rtl/verilog2/
68	- added decimal float compare	robfinch	832d 06h	/ft816float/trunk/rtl/verilog2/

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Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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