URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 51

Rev	Log message	Author	Age	Path
51	- got rid of 'DF0'	robfinch	1295d 03h	/ft816float/trunk/rtl/verilog2/
50	- added decimal floating-point adder	robfinch	1295d 11h	/ft816float/trunk/rtl/verilog2/
49	- pipelining	robfinch	1315d 16h	/ft816float/trunk/rtl/verilog2/
48	- refactoring to use packages	robfinch	1340d 00h	/ft816float/trunk/rtl/verilog2/
35	- additional pipelining in divider - radix4 primitive	robfinch	1555d 14h	/ft816float/trunk/rtl/verilog2/
34	- add pipeline stage in divider	robfinch	1555d 17h	/ft816float/trunk/rtl/verilog2/
33	- mult114 for FMA	robfinch	1808d 01h	/ft816float/trunk/rtl/verilog2/
32	- FMA, test bench for FMA	robfinch	1808d 01h	/ft816float/trunk/rtl/verilog2/
31	- preserve nan sign in addsub	robfinch	1808d 13h	/ft816float/trunk/rtl/verilog2/
30	- move load signal to bottom	robfinch	1824d 08h	/ft816float/trunk/rtl/verilog2/
29	- refactor with FPWID and EXTRA_BITS - Nan propagation	robfinch	1824d 16h	/ft816float/trunk/rtl/verilog2/