URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 57

Rev	Log message	Author	Age	Path
57	- decimal floating-point IEEE format encode/decode	robfinch	1268d 14h	/ft816float/trunk/rtl/verilog2/
56	- decimal square root function	robfinch	1293d 14h	/ft816float/trunk/rtl/verilog2/
55	- add storage format - parameterization	robfinch	1294d 06h	/ft816float/trunk/rtl/verilog2/
54	- add decimal float divider	robfinch	1294d 20h	/ft816float/trunk/rtl/verilog2/
53	- added decimal floating-point multiplier	robfinch	1296d 00h	/ft816float/trunk/rtl/verilog2/
51	- got rid of 'DF0'	robfinch	1296d 03h	/ft816float/trunk/rtl/verilog2/
50	- added decimal floating-point adder	robfinch	1296d 11h	/ft816float/trunk/rtl/verilog2/
49	- pipelining	robfinch	1316d 16h	/ft816float/trunk/rtl/verilog2/
48	- refactoring to use packages	robfinch	1341d 00h	/ft816float/trunk/rtl/verilog2/
35	- additional pipelining in divider - radix4 primitive	robfinch	1556d 14h	/ft816float/trunk/rtl/verilog2/
34	- add pipeline stage in divider	robfinch	1556d 17h	/ft816float/trunk/rtl/verilog2/
33	- mult114 for FMA	robfinch	1809d 01h	/ft816float/trunk/rtl/verilog2/
32	- FMA, test bench for FMA	robfinch	1809d 01h	/ft816float/trunk/rtl/verilog2/
31	- preserve nan sign in addsub	robfinch	1809d 13h	/ft816float/trunk/rtl/verilog2/
30	- move load signal to bottom	robfinch	1825d 08h	/ft816float/trunk/rtl/verilog2/
29	- refactor with FPWID and EXTRA_BITS - Nan propagation	robfinch	1825d 16h	/ft816float/trunk/rtl/verilog2/