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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 79

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Rev Log message Author Age Path
79 - fix sticky infinity robfinch 553d 19h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function		 robfinch 554d 06h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 556d 06h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 556d 12h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 664d 05h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 835d 05h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 835d 08h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 843d 04h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 843d 11h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 847d 10h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 847d 13h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 847d 16h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 847d 16h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 847d 16h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 848d 05h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 848d 07h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 848d 11h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1109d 16h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1251d 05h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1276d 05h /ft816float/trunk/rtl/verilog2/

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