URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 83

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Rev	Log message	Author	Age	Path
83	- sign of zero is positive	robfinch	548d 12h	/ft816float/trunk/rtl/verilog2/
82	- improved divider	robfinch	548d 12h	/ft816float/trunk/rtl/verilog2/
81	- timing delay on divide - change adder in multiply	robfinch	548d 22h	/ft816float/trunk/rtl/verilog2/
80	- improve decimal float divide	robfinch	549d 03h	/ft816float/trunk/rtl/verilog2/
79	- fix sticky infinity	robfinch	550d 11h	/ft816float/trunk/rtl/verilog2/
78	- BCD subtraction - scaleb function	robfinch	550d 23h	/ft816float/trunk/rtl/verilog2/
76	- adjust 9 to 7	robfinch	552d 23h	/ft816float/trunk/rtl/verilog2/
75	- add triple precision decimal float	robfinch	553d 04h	/ft816float/trunk/rtl/verilog2/
74	- added single precision combo logic only version of FMA	robfinch	660d 22h	/ft816float/trunk/rtl/verilog2/
73	- fix Karatsuba carry chain bug	robfinch	831d 22h	/ft816float/trunk/rtl/verilog2/
72	- fix: mult32x32 prod high order bits	robfinch	832d 00h	/ft816float/trunk/rtl/verilog2/
71	- added decimal float reciprocal estimate	robfinch	839d 21h	/ft816float/trunk/rtl/verilog2/
70	- fix carry out for BCD add / sub	robfinch	840d 04h	/ft816float/trunk/rtl/verilog2/
68	- added decimal float compare	robfinch	844d 02h	/ft816float/trunk/rtl/verilog2/
67	- adding decimal float divide	robfinch	844d 06h	/ft816float/trunk/rtl/verilog2/
66	- BCD arith additions	robfinch	844d 08h	/ft816float/trunk/rtl/verilog2/
65	-update dfdiv / dfmul	robfinch	844d 08h	/ft816float/trunk/rtl/verilog2/
64	- add multiply 128 - fix exponent bias	robfinch	844d 08h	/ft816float/trunk/rtl/verilog2/
62	- fix overflow status - license comment	robfinch	844d 21h	/ft816float/trunk/rtl/verilog2/
60	- decimal float <-> int converters	robfinch	844d 23h	/ft816float/trunk/rtl/verilog2/

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Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 83

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