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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 84

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Rev Log message Author Age Path
84 - improve DPD divider robfinch 536d 17h /ft816float/trunk/rtl/verilog2/
83 - sign of zero is positive robfinch 536d 20h /ft816float/trunk/rtl/verilog2/
82 - improved divider robfinch 536d 20h /ft816float/trunk/rtl/verilog2/
81 - timing delay on divide
- change adder in multiply		 robfinch 537d 06h /ft816float/trunk/rtl/verilog2/
80 - improve decimal float divide robfinch 537d 11h /ft816float/trunk/rtl/verilog2/
79 - fix sticky infinity robfinch 538d 19h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function		 robfinch 539d 07h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 541d 07h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 541d 12h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 649d 06h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 820d 06h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 820d 08h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 828d 05h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 828d 12h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 832d 10h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 832d 14h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 832d 16h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 832d 16h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 832d 16h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 833d 05h /ft816float/trunk/rtl/verilog2/

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