OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 86

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
86 - improve divider *10 robfinch 547d 22h /ft816float/trunk/rtl/verilog2/
85 - improve divider *10 robfinch 547d 22h /ft816float/trunk/rtl/verilog2/
84 - improve DPD divider robfinch 548d 01h /ft816float/trunk/rtl/verilog2/
83 - sign of zero is positive robfinch 548d 03h /ft816float/trunk/rtl/verilog2/
82 - improved divider robfinch 548d 03h /ft816float/trunk/rtl/verilog2/
81 - timing delay on divide
- change adder in multiply		 robfinch 548d 13h /ft816float/trunk/rtl/verilog2/
80 - improve decimal float divide robfinch 548d 19h /ft816float/trunk/rtl/verilog2/
79 - fix sticky infinity robfinch 550d 02h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function		 robfinch 550d 14h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 552d 14h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 552d 19h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 660d 13h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 831d 13h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 831d 16h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 839d 12h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 839d 19h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 843d 18h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 843d 21h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 843d 23h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 843d 23h /ft816float/trunk/rtl/verilog2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.