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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 88

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Rev Log message Author Age Path
88 - DPFTrunc() function robfinch 655d 06h /ft816float/trunk/rtl/verilog2/
86 - improve divider *10 robfinch 670d 08h /ft816float/trunk/rtl/verilog2/
85 - improve divider *10 robfinch 670d 08h /ft816float/trunk/rtl/verilog2/
84 - improve DPD divider robfinch 670d 11h /ft816float/trunk/rtl/verilog2/
83 - sign of zero is positive robfinch 670d 13h /ft816float/trunk/rtl/verilog2/
82 - improved divider robfinch 670d 14h /ft816float/trunk/rtl/verilog2/
81 - timing delay on divide
- change adder in multiply		 robfinch 670d 23h /ft816float/trunk/rtl/verilog2/
80 - improve decimal float divide robfinch 671d 05h /ft816float/trunk/rtl/verilog2/
79 - fix sticky infinity robfinch 672d 13h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function		 robfinch 673d 00h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 675d 00h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 675d 06h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 782d 23h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 953d 23h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 954d 02h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 961d 22h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 962d 05h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 966d 04h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 966d 08h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 966d 10h /ft816float/trunk/rtl/verilog2/

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