OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 31

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
31 Bug fix. Interrupts were also asserted when condition was not met. lampret 7894d 03h /gpio/tags/rel_12/rtl/verilog/
29 Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. lampret 7901d 04h /gpio/tags/rel_12/rtl/verilog/
27 negedge flops are enabled by default. lampret 8090d 07h /gpio/tags/rel_12/rtl/verilog/
26 Removed zero padding as per Avi Shamli suggestion. lampret 8144d 04h /gpio/tags/rel_12/rtl/verilog/
25 Ports changed per Ran Aviram suggestions. lampret 8144d 04h /gpio/tags/rel_12/rtl/verilog/
24 Interrupt is asserted only when an input changes (code patch by Jacob Gorban) lampret 8148d 22h /gpio/tags/rel_12/rtl/verilog/
23 Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. lampret 8202d 06h /gpio/tags/rel_12/rtl/verilog/
22 Fixed two typos. lampret 8222d 08h /gpio/tags/rel_12/rtl/verilog/
21 Added RGPIO_INTS. lampret 8222d 08h /gpio/tags/rel_12/rtl/verilog/
20 Fixing style. lampret 8235d 05h /gpio/tags/rel_12/rtl/verilog/
19 Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) lampret 8235d 18h /gpio/tags/rel_12/rtl/verilog/
17 Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. lampret 8262d 23h /gpio/tags/rel_12/rtl/verilog/
15 Fixed wb_err_o. lampret 8277d 23h /gpio/tags/rel_12/rtl/verilog/
14 Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. lampret 8320d 06h /gpio/tags/rel_12/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.