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[/] [gpio/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 65

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Rev Log message Author Age Path
65 New directory structure. root 5602d 10h /gpio/tags/rel_15/rtl/verilog/
64 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7299d 23h /gpio/tags/rel_15/rtl/verilog/
62 Reorganize core, add synchronization flops. simont 7299d 23h /gpio/tags/rel_15/rtl/verilog/
60 Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec andreje 7372d 00h /gpio/tags/rel_15/rtl/verilog/
56 added ECLK and NEC registers, all tests passed. gorand 7511d 19h /gpio/tags/rel_15/rtl/verilog/
52 ifndef directive is not supported by all tools. simons 7527d 15h /gpio/tags/rel_15/rtl/verilog/
36 bug fixed. all tests passed. gorand 7548d 09h /gpio/tags/rel_15/rtl/verilog/
34 added support for 8-bit access to registers. gorand 7552d 18h /gpio/tags/rel_15/rtl/verilog/
31 Bug fix. Interrupts were also asserted when condition was not met. lampret 7905d 10h /gpio/tags/rel_15/rtl/verilog/
29 Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. lampret 7912d 11h /gpio/tags/rel_15/rtl/verilog/
27 negedge flops are enabled by default. lampret 8101d 14h /gpio/tags/rel_15/rtl/verilog/
26 Removed zero padding as per Avi Shamli suggestion. lampret 8155d 11h /gpio/tags/rel_15/rtl/verilog/
25 Ports changed per Ran Aviram suggestions. lampret 8155d 11h /gpio/tags/rel_15/rtl/verilog/
24 Interrupt is asserted only when an input changes (code patch by Jacob Gorban) lampret 8160d 04h /gpio/tags/rel_15/rtl/verilog/
23 Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. lampret 8213d 13h /gpio/tags/rel_15/rtl/verilog/
22 Fixed two typos. lampret 8233d 15h /gpio/tags/rel_15/rtl/verilog/
21 Added RGPIO_INTS. lampret 8233d 15h /gpio/tags/rel_15/rtl/verilog/
20 Fixing style. lampret 8246d 12h /gpio/tags/rel_15/rtl/verilog/
19 Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) lampret 8247d 01h /gpio/tags/rel_15/rtl/verilog/
17 Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. lampret 8274d 06h /gpio/tags/rel_15/rtl/verilog/

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