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[/] [ha1588/] - Rev 38

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Rev	Log message	Author	Age	Path
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4455d 19h	/ha1588/
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4455d 23h	/ha1588/
36	TSU testbench is now self-checking. Test result is reported at end of simulation.	edn_walter	4456d 18h	/ha1588/
35	Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets.	edn_walter	4457d 17h	/ha1588/
34	Added LGPL file header to all copyrighted files.	edn_walter	4457d 19h	/ha1588/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4457d 21h	/ha1588/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4457d 23h	/ha1588/
31	Added hand-shaking for the TSU data reading.	edn_walter	4458d 16h	/ha1588/
30	Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit	edn_walter	4458d 17h	/ha1588/
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4458d 17h	/ha1588/
28	Before changing TSU packet parser datapath width from 32b to 8b.	edn_walter	4458d 23h	/ha1588/
27	Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s.	edn_walter	4458d 23h	/ha1588/
26	Updated test case.	edn_walter	4460d 18h	/ha1588/
25	Updated SOPC Builder component and example system.	edn_walter	4461d 17h	/ha1588/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4461d 18h	/ha1588/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4462d 12h	/ha1588/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4462d 16h	/ha1588/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4463d 13h	/ha1588/
20	Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder.	edn_walter	4467d 17h	/ha1588/
19	Added pipeline registers to Real Time Clock module to improve timing.	edn_walter	4467d 17h	/ha1588/

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[/] [ha1588/] - Rev 38

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