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Subversion Repositories ha1588

[/] [ha1588/] - Rev 76

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Rev Log message Author Age Path
76 Prepare for adding new system integration tool support. ash_riple 2405d 10h /ha1588/
75 Added empty folder sys/xilinx_ipi. ash_riple 2405d 11h /ha1588/
74 Changed the name of system integration folders, going to add xilinx IPI support for Vivado. ash_riple 2405d 11h /ha1588/
73 Corrected AXI4 wrapper timing bug.
Added system-level instantiation examples for XPS and Qsys.		 ash_riple 3651d 14h /ha1588/
72 Minor changes. ash_riple 3977d 10h /ha1588/
71 Added architecture description in the doc folder. ash_riple 3977d 12h /ha1588/
70 Updated Altera Qsys instantiation script. ash_riple 4133d 09h /ha1588/
69 Fixed the negative period adjustment bug. ash_riple 4134d 14h /ha1588/
68 Refined the vendor specific IP instanttiation. Now DCFIFO is instantiated as a vendor specific IP in PAR directory. ash_riple 4134d 17h /ha1588/
67 Updated the WishBone IP top and Qsys IP top. ash_riple 4136d 10h /ha1588/
66 Added IP instantiation support for: QSys, XPS and WishBone. ash_riple 4137d 10h /ha1588/
65 Added WishBone compatible wrapper for register access. ash_riple 4141d 14h /ha1588/
64 Added PTPv2 timing analyzer tool. ash_riple 4143d 11h /ha1588/
63 Updated the simulation script under Linux. ash_riple 4146d 15h /ha1588/
62 Removed environment variable settings in the simulation script under Windows. ash_riple 4146d 15h /ha1588/
61 Made different scripts for top-level simulation to run under Linux. ash_riple 4146d 16h /ha1588/
60 Made different scripts for top-level simulation to run under Linux. ash_riple 4146d 16h /ha1588/
59 Made different scripts for top-level simulation to run under Windows. ash_riple 4146d 16h /ha1588/
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4419d 13h /ha1588/
57 Added parameters of frame header constants for packet parsing. edn_walter 4419d 15h /ha1588/

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