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[/] [ha1588/] [tags/] [v1p0/] [rtl/] [top/] - Rev 28

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28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 4497d 20h /ha1588/tags/v1p0/rtl/top/
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4497d 20h /ha1588/tags/v1p0/rtl/top/
25 Updated SOPC Builder component and example system. edn_walter 4500d 14h /ha1588/tags/v1p0/rtl/top/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4502d 10h /ha1588/tags/v1p0/rtl/top/
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 4506d 14h /ha1588/tags/v1p0/rtl/top/
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4506d 14h /ha1588/tags/v1p0/rtl/top/
17 Updated reg.v content. edn_walter 4507d 08h /ha1588/tags/v1p0/rtl/top/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 4513d 10h /ha1588/tags/v1p0/rtl/top/

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