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[/] [ha1588/] [tags/] [v1p0/] [sim/] [rtc/] - Rev 28

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28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 4474d 01h /ha1588/tags/v1p0/sim/rtc/
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4482d 19h /ha1588/tags/v1p0/sim/rtc/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 4489d 14h /ha1588/tags/v1p0/sim/rtc/
3 Added function block RTC and its unit test. ash_riple 4507d 13h /ha1588/tags/v1p0/sim/rtc/

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